SET Immune Spaceborne CVSL and CVSL Circuits
نویسنده
چکیده
In order to design radiation-hardened LSIs for space applications, single event transient (SET) effects on cascade voltage switch logic (CVSL) circuits have been investigated using SPICE. Static CVSL and clocked CVSL (CVSL) circuits have been successfully fabricated utilizing a double polysilicon double metal N-well CMOS technology. A CVSL half adder, a CVSL half adder and a CVSL full adder have confirmed to function correctly by the chip measurements. SET simulation results have confirmed that the CVSL and CVSL circuits have increased tolerance to SET. SET tolerance for the CVSL and CVSL circuits is compared to that for the conventional CMOS circuits, showing that the CVSL and CVSL circuits are candidates for a SET tolerant spaceborne circuit. CVSL circuits are more than 200 times harder and CVSL circuits are ten times harder than conventional CMOS circuits. KeywordsCVSL; CVSL; SET; Radiation; Simulation
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